About the Role
As physical design engineer, you will be responsible for the digital implementation of TSS’s IPs and SoC to achieve the highest performance per watt in leading edges process technologies You will define the methodology for synthesis, place and route, STA, EMIR, LEC, DRC and LVS, and also take full ownership of implementing our RTL design to final GDSII. This a great opportunity for any engineer who wants to develop expertise on all aspects of physical design.
Responsibilities
Define top-level floorplan of IP and SoC
Work with RTL designers to define timing constraints
Optimize and execute physical synthesis flow
Optimize and execute low-power place and route methodology
Static timing analysis and sign-off
Static and dynamic electromigration and IR analysis (EMIR)
Physical verification (DRC, ERC, LVS) at IP and SoC level
Formal verification including LEC and CDC
Power analysis and optimization
Timing and physical models generation
Develop implementation guidelines for customers
Customer support relating to IP integration
Requirements
Bachelor/Master in Electrical or Computer Engineering
Extensive physical design experience in complex ASIC
Hands-on experience in chip level integration
Deep understanding of timing constraints and clock domain crossing (CDC)
Knowledge of full ASIC design flow including synthesis, place and route, timing and power optimization, etc
Proficient in scripting languages (Perl, Python, Tcl, etc)
Excellent communication and problem solving skills