At The Six Semiconductor (The Six Semi), our vision is to offer best in class mixed-signal IP combined with exceptional service, thus enabling SOC companies to bring their product to market in highest quality and shortest time.  When compared to competitors, our IP achieve higher performance at lower power and area, while offering the flexibility and ease of integration to our customers.  Our team is highly experienced with a long list of achievements and accomplishments in the semiconductor industry.

We strongly believe in a culture of transparency and trust.  By ensuring important information are readily accessible, we entrust our staff to make the best decisions resulting in superior products and customer service.  We also foster a continuous learning environment with an emphasis on a well-rounded career.  Our compensation and benefits package is very competitive as we believe best talents should be rewarded accordingly.  We welcome you to be part of this fast-growing team making an impact in the industry.

As a senior digital verification engineer at The Six Semi, you will be responsible for  the overall verification strategy and infrastructure for our memory PHY IPs and associate prototype silicons.  You will be the lead verification engineer for our various projects, involving in resource planning, test plan definition, execution, progress report, and final sign-off.  You will work closely with the design team to resolve design and verification issues and to ensure concise and efficient communication between the teams.


  • Define overall verification strategy and methodology for the whole company
  • Define verification environment for memory PHY IPs and testchips 
  • Develop test plan and coverage metrics for functional coverage of memory PHY IPs and testchips
  • Plan verification resource and schedule
  • Develop verification components and checker for timing sensitive interface
  • Execute test plan, debug failures, monitor progress and achieve full functional and code coverage
  • Develop functional coverage checkpoints
  • Create sign-off checklist and review overall verification results for tape-out
  • Customer engagement for verification related questions and issues


  • Bachelor/Master in Electrical or Computer Engineering
  • Expert knowledge in Verilog, SystemVerilog, UVM, direct and random verification
  • Extensive design verification experience using SystemVerilog in UVM
  • Experience with design or verification of high-speed interfaces such as DDR and PCIE
  • Proficient in one or more scripting and programming languages (Perl, Python, C, etc)